`include "common_header.verilog"

//  *************************************************************************
//   File : rand2step.v
//  *************************************************************************
//   This program is controlled by a written license agreement.
//   Unauthorized Reproduction or Use is Expressly Prohibited. 
// 
//  Copyright (c) 2005 Morethanip GmbH
//  info@morethanip.com
//  *************************************************************************
//  Version: $Id: rand2step.v,v 1.3 2006/06/16 15:55:50 mr Exp $ 
//  Author : Muhammad Anisur Rahman
//  *************************************************************************
//   Description:
// 
//   PCS Idle Randomizer with two steps per clock cycle
// 
//  *************************************************************************

module rand2step (

   reset,
   clk,
`ifdef USE_CLK_ENA
   clk_ena,
`endif    
   lower_col_a,
   load,
   code_sel,
   a_cnt);
   
input   reset;                  //  active high
input   clk; 
`ifdef USE_CLK_ENA
input   clk_ena;
`endif
input   lower_col_a;
input   load; 
output  [1:0] code_sel;         //  r used as code selector between |R| or |K|
output  [1:0] a_cnt;            //  these LSB 4 bits are loaded to the down counter

wire    [1:0] code_sel; 
wire    [1:0] a_cnt; 
reg    [4:0] count; 
wire    [3:0] x_lsb; 
reg     [1:0] a_cnt1; 
reg     [4:0] count_load; 

assign a_cnt = a_cnt1; 
//assign count = count_load - 5'h 6; 

always @(count_load or lower_col_a)
   begin: process_0
                
        if(lower_col_a==1'b 1)
        begin
        count   = count_load-5'h 3;
        end
        else
        begin
        count   = count_load-5'h 2;
        end                               
   end

lfsr2step U_LFSR (

          .reset(reset),
          .clk(clk),
        `ifdef USE_CLK_ENA
          .clk_ena(clk_ena),
        `endif            
          .lsb(code_sel),
          .x_lsb(x_lsb));
          
always @(posedge clk or posedge reset)
   begin : process_1
   if (reset == 1'b 1)
      begin
      count_load <= {5{1'b 1}};   
      a_cnt1     <= 2'b 11;   
      end
   else
      begin
        `ifdef USE_CLK_ENA
          if(clk_ena == 1'b 1)
          begin
        `endif              
              if (load == 1'b 1)
                 begin
                 count_load <= {1'b 1, x_lsb};   
                 end
              else if (count > 5'h1 )
                 begin
                 count_load <= count_load - 5'h 2;   
                 end
              if (load == 1'b 1 | count > 5'h 3)
                 begin
                 a_cnt1 <= 2'b 11;   
                 end
              else if (count == 5'h 3 & a_cnt1 == 2'b 11 )
                 begin
                 a_cnt1 <= 2'b 01;   
                 end
              else
                 begin
                 a_cnt1 <= 2'b 00;   
                 end
        `ifdef USE_CLK_ENA
           end
        `endif      
      
      end
   end

endmodule // module rand2step